1. Field of the Invention
The present invention generally relates to microprocessors and, more particularly, to a microprocessor having a multiple stage shifter which selectively performs pre-processing and shift/rotate/pass operations to produce improved performance of shift/rotate operations thereby.
2. Description of Related Art
Digital circuitry for performing arithmetic operations such as shift and/or rotate operations have long been known in the art. In a shift operation, data stored in a storage device, commonly referred to as a shift register, is moved relative to the boundaries of the device. An arithmetic shift right effects a divide by 2 operation while an arithmetic shift left effects a multiply by 2 operation. In a circular shift operation, also known as a rotate, the rightmost and leftmost positions in the shift register are treated as being adjacent during the shift. A rotate operation may be a rotate left (or "ROL") operation in which all of the bits of an operand are shifted left by one or more positions and the most significant bits are shifted around to become the least significant bits or a rotate right (or "ROR") operation in which all of the bits of the operand shifted right by one or more positions and the least significant bits are shifted around to become the most significant bits.
Digital circuitry to perform the aforementioned arithmetic operations is commonly found in the execution unit of a microprocessor. In 32-bit microprocessor architectures, however, the circuitry becomes more cumbersome due to an increase in the number of types of rotate operations which may be performed. Specifically, the size of the operand to be rotated may be byte, word or double word. To rotate a byte size operand, bits 0 and 7 must be interconnected. To rotate a word size operand, bits 0 and 15 must be interconnected. Finally, to rotate a double word size operand, bit 0 and 31 must be interconnected.
One proposed solution to this problem involves providing a conditioning unit which pre-processes byte and/or word size operands before they are provided to the shift unit for the rotate operation. More specifically, it has been proposed that the contents of byte or word sized operands are replicated or "smeared" into the other bytes of the 32-bit register. For example, if a byte size operand is placed into byte 0 (bits 0-7) of a 4 byte (32 bit) register, the contents of byte 0 are smeared into bytes 1, 2 and 3. Then, to rotate byte 0, the only connection required is between bits 0 and 31. When the rotate operation is complete, byte 0 holds the result while bytes 1, 2 and 3 are discarded.
While the proposed solution would successfully reduce the number of interconnections between the various bits of the shift register, such a reduction was achieved only at the cost of adding an additional unit to precondition selected operands. Such a preconditioning unit may be seen by reference to U.S. Pat. No. 5,379,240 to Byrne.
Unfortunately, preconditioning units often add to the overhead attributable to arithmetic operations. Thus, it can be readily seen from the foregoing that it would be desirable to provide a shift and rotate circuit which eliminates the need for a preconditioning unit without increasing the number of interconnections required to perform rotate operations on the various sized operands used in arithmetic operations in 32-bit architectures. It is, therefore, the object of this invention to provide a shift and rotate circuit uniquely configured to both reduce the number of interconnections required to perform rotate operations and eliminate the preconditioning unit.